The present invention generally relates to semiconductor devices and more particularly to a semiconductor integrated circuit device including a stressed semiconductor device that achieves improved operational speed as a result of stressing and fabrication process thereof.
With progress in the technology of device miniaturization, it is now becoming possible to produce ultrafine and ultra high-speed semiconductor devices having a gate length of 100 nm or less.
With such ultrafine and ultrahigh speed transistors, the area of the channel region right underneath the gate electrode is very small as compared with conventional semiconductor devices, and thus, mobility of electrons or holes traveling through the channel region is influenced heavily by the stress applied to the channel region. Thereupon, various attempts have been made for improving the operational speed of the semiconductor device by optimizing the stress applied to the channel region.